This invention relates to the fabrication of semiconductor devices. More particularly, the present invention relates to a method for fabricating vertical surround gate structures in a semiconductor device array.
In semiconductor device applications, conventional planar transistors have the most mature integration process. However, in memory applications, particularly access devices (or selectors), reduction of device footprint is essential to improve memory density. Planar transistor performance is generally restricted by channel width and length. Reducing channel width or length can improve memory density at the cost of degraded device performance.
Vertical surround gate devices have become an attractive design choice for memory applications. In vertical surround gate devices the current flow is oriented in a vertical direction, providing many advantages to area efficiency. However, many current integration processes for vertical surround gate structures are not easily compatible with standard CMOS integration. Specifically, many current applications of double patterning techniques for channel, source, and drain formation are disruptive to the standard CMOS thermal cycle. Additionally, from a cost efficient perspective, it is desirable to integrate the vertical surround gate structures with a minimum number of additional masks.